Functionalized MXene ink enables environmentally stable printed electronics


Properties of AD-MXene

As illustrated in Fig. 1a, the AD-MXene ink for EHD printing was prepared through facile mixing of aqueous dispersion of MXene with ethanol dispersion of ADOPA ligand at room temperature for around one hour and subsequent replacement of solvent with ethanol via centrifugation. The ADOPA ligand spontaneously adsorbed onto MXene due to its catechol head strong hydrogen-bonding and π-electron interactions with MXene surface functional groups, and the hydrophobic tail of ADOPA ligand enables the excellent dispersion of obtained AD-MXene in ethanol. The X-ray photoelectron spectroscopy (XPS) spectra for the Ti 2 p, O 1 s, C 1 s, and N 1 s core levels of AD-MXene and pristine MXene are shown in Fig. 1b and Supplementary Fig. 1. Due to primary amine moiety in ADOPA, AD-MXene shows a clear peak around 399.9 eV in the N 1 s region, confirming the attachment of ADOPA (Fig. 1b). To investigate further the interlayer structure and alignment of MXene sheets in the film, the X-ray diffraction (XRD) patterns of both pristine MXene and AD-MXene films were recorded as shown in Supplementary Fig. 2. The (002) peak shift from 7.32° to 6.38° was observed, corresponding to a d-spacing expansion from 1.22 nm to 1.36 nm, resulting from attached ligands. Compared to pristine MXene with poor dispersion properties in ethanol, AD-MXene shows excellent dispersion, as shown in Fig. 1c. The field emission scanning electron microscope (FE-SEM) image in Fig. 1d shows a representative AD-MXene flake from a batch with an average lateral size of 1.81 μm. Due to the enhanced hydrophobicity after ADOPA functionalization, our previous study has shown that AD-MXene is environmentally stable for an extended time, compared to pristine waterborne MXene, which is otherwise susceptible to water uptake and subsequent environmental degradation39. This has also been proven to be true in electronic devices with AD-MXene exposed to the surface, where a recent study shows that chemical sensors based on AD-MXene retained their performance for over 6 weeks of exposure in ambient environments49.

Fig. 1: Synthesis and characterization of AD-MXene.
figure 1

a Schematic illustration of the general reaction procedure for preparing AD-MXene. b N 1 s XPS spectrum of AD-MXene. c Digital photograph of AD-MXene and pristine MXene dispersions in ethanol. d FE-SEM image of a single AD-MXene flake.

Electrical properties of EHD-printed AD-MXene electrodes

As shown in Fig. 2a, the as-prepared ethanol-based AD-MXene ink was loaded into EHD printing equipment and then ejected through the nozzle tip by applying an electric field between the nozzle and the substrate. The printing conditions were optimized by examining the jetting behavior and tuning the working distance (distance from the nozzle tip to the substrate) and the applied electric field. Four jetting behaviors, such as dripping, micro-dripping, cone-jet, and multi-jet, were noticed when the working distance and applied voltage were tuned in the ranges of 100–600 μm and 0.5–3.0 kV, respectively (Fig. 2b). The AD-MXene ink was printed into line-shaped patterns on a SiO2/Si wafer at conditions optimized for uniform jetting in the stable cone-jet mode. These precise conditions encompassed a nozzle size of 185 μm, a printing speed of 10 mm s−1, a controlled flow rate of 1.3 μL min–1, and an applied voltage of 1.3 kV, all sustained at a working distance of 450 µm.

Fig. 2: EHD printing of AD-MXene electrodes and their current-voltage characteristics.
figure 2

a Schematic showing the EHD printing of AD-MXene inks from a nozzle. The inset shows the optical microscope image of AD-MXene ink drops at the edge of the nozzle tip during the cone-jet mode of the EHD printing process. b Chart showing the EHD printing modes as a function of working distance and applied voltage. c Current–voltage characteristic curves of AD-MXene electrodes fabricated by 1–10 cycles of EHD printing. d Current-voltage characteristic curves of AD-MXene electrodes with 1–30 mm channel length (with 10 cycles of EHD printing). e View through an AD-MXene electrode printed in a square spiral geometry on glass.

Optical microscope and cross-sectional FE-SEM images revealed the increased thickness of AD-MXene lines with increased printing cycles from 1 to 10 (Supplementary Figs. 3, 4). Further, atomic force microscopy (AFM) analysis revealed the gradual increase of average surface roughness (Ra) of AD-MXene lines with an increase in the number of printing cycles, and the Ra was observed to be 7.8 nm for lines fabricated with 10 printing cycles (Supplementary Fig. 5). Characteristic current-voltage curves of AD-MXene electrodes revealed that the increase in the thickness of lines (or number of printing cycles) enabled the enhanced current flow. In contrast, the increase in channel length decreased the current (Fig. 2c, d). Therefore, the EHD printing of AD-MXene with a controlled number of printing cycles and channel lengths may enable the facile fabrication of conductive wires/resistors of circuitries. The electrical conductivity of the AD-MXene electrode (length = 1 mm, width = 320 μm, and thickness = 190 nm) fabricated by 10 cycles of printing was observed to be 5579 S cm−1, which was almost equal to that of the AD-MXene film fabricated using vacuum-assisted filtration. This is because the ADOPA ligands facilitated the alignment of AD-MXene flakes during the EHD printing process and enabled the printed AD-MXene electrodes to have excellent electrical conductivity (Supplementary Fig. 4). We hypothesize that the ligand’s planar alignment and strong π-electron interaction with the MXene surface facilitated the inter-flake electron transport; as a result, the AD-MXene films exhibited electrical conductivity almost equal to that of pristine MXene film despite having ADOPA ligands as intercalants39. Notably, the conductivity of AD-MXene electrode (5579 S cm−1) is considerably higher than previously reported poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) electrodes (0.2–1200 S cm–1)50, reduced graphene oxide-based electrodes (590 S cm–1)51, and pristine MXene electrode (2600 S cm–1)23. Besides, printing AD-MXene electrodes is more favorable as it doesn’t require post-treatments, unlike other metal-based (Cu, Ag, Zn, etc.) inks52,53,54. The AD-MXene electrode designed in the square spiral pattern through continuous writing with the AD-MXene ink revealed the compatibility of AD-MXene ink for EHD printing of complex circuits (Fig. 2e).

Performance of AD-MXene as electrodes of TFTs

The excellent compatibility of the AD-MXene ink for EHD printing and the high electrical conductivity of printed AD-MXene lines motivated us to investigate the effectiveness of AD-MXene as electrical contacts of TFTs. Therefore, we fabricated a TFT, wherein the AD-MXene was printed as source and drain electrodes on the ZTO active material deposited on SiO2/Si substrate (Fig. 3a). ZTO was selected as an active layer due to its cost-effectiveness, solution processability, and potential as alternative to expensive indium-based counterparts55. Fig. 3b shows the transfer characteristics of TFTs prepared with AD-MXene electrodes deposited at different numbers of EHD printing cycles. All devices showed typical n-type transfer characteristics during ± 40 V of gate voltage (VG) sweep (source to drain voltage (VD) = 40 V). The increased number of AD-MXene electrode printing cycles enhanced the transfer performance of TFTs due to the improvement in electrical conductivity through the formation of denser network of AD-MXene electrode (Fig. 3b). The field-effect mobility (μFET) values were determined from ID1/2 vs. VG plots by following the equation: ID = μFETCiW(2 L)−1(VGVth)2, where ID, Ci, W, L, and Vth are drain current, areal capacitance, channel width, channel length, and threshold voltage, respectively. The μFET of devices gradually increased with an increase in the number of AD-MXene printing cycles or the thickness of MXene electrodes (Fig. 3c). For comparison, TFTs with vacuum-deposited Au and Al electrodes were also fabricated, and their performances were compared with that of AD-MXene devices (Fig. 3d–f). Figure 3e compares the transfer characteristics of ZTO-based TFT devices prepared with different source/drain electrodes (AD-MXene, Au, and Al). The ZTO TFT fabricated with AD-MXene source/drain electrodes exhibited better transfer characteristics than those fabricated with vacuum-deposited Al and Au electrodes. Hysteresis (the variation in the OFF-to-ON sweeping transfer curve compared to the ON-to-OFF transfer curve) was not observed for devices comprising Al and AD-MXene as source/drain electrodes. In contrast, the device with Au as source/drain electrodes exhibited poor electrical performance with hysteresis (Fig. 3e). Remarkably, the AD-MXene based TFT yielded considerably higher μFET of 3.24 cm2 V–1 s–1 than those based on Al (2.61 cm2 V–1 s–1) and Au (1.75 cm2 V–1 s–1) electrodes (Fig. 3f). The off-current value of the AD-MXene based TFT was somewhat higher than that of the Au device. This was probably attributed to a combination of factors such as gate leakage, subthreshold conduction, and trap states rather than the properties of the electrode material, all of which can be sufficiently optimized by device structure design and scale control of the printed electrode. Contact resistances of TFTs with different electrodes were extracted by the transfer length method from the width-normalized total resistance (RtotW) of TFTs as a function of channel length shown in Supplementary Fig. 6. Although the RtotW showed a linear relationship with the channel length for all TFTs, AD-MXene electrodes caused low resistance as compared to Au and Al electrodes. Therefore, given that the crystalline morphology underneath the ZTO semiconductor layer was the same for all electrodes, the observed differences in μFET values of devices must have originated due to the changes in contact resistances at the interface of channel and electrode. In other words, we infer that the solution-processed AD-MXene electrodes provided an excellent interface with the ZTO active layer deposited through the same solution route compared to vacuum-deposited Au and Al electrodes.

Fig. 3: Transfer characteristics and mobilities of TFTs with different electrodes.
figure 3

a Schematic representation and an optical microscope image of top-contact TFT with EHD printed AD-MXene electrodes. Transfer characteristics (b) and μFET values (c) of TFTs employing AD-MXene electrodes produced with various numbers of EHD printing cycles. d Schematic representation of top-contact TFTs employing vacuum-deposited Au and Al electrodes. Transfer characteristics (e) and μFET values (f) of TFTs employing AD-MXene, Al, and Au electrodes. The error bars in this figure represent the standard deviations of five different measurements from the same data.

Performance of TFTs with different dielectric layers

The superiority and universality of AD-MXene electrodes was further demonstrated by utilizing them as gate, source, and drain electrodes in top-gate top-contact TFTs with PVDF-HFP and FPVDF-HFP dielectrics (Fig. 4). Insulating characteristics of PVDF-HFP and FPVDF-HFP dielectrics were evaluated before their integration in TFTs. To this end, metal-insulator-metal (MIM) capacitors with device structures of AD-MXene/PVDF-HFP/AD-MXene and AD-MXene/FPVDF-HFP/AD-MXene were fabricated by EHD-printing and their leakage current densities were measured (Supplementary Fig. 7a, b). The observed leakage current densities below 10−8 A cm−2 at an applied electric field strength of 4 MV cm−1 for both devices revealed the excellent insulation properties of PVDF-HFP and FPVDF-HFP dielectrics. Furthermore, the areal capacitances of PVDF-HFP and FPVDF-HFP dielectrics at 1 kHz were measured to be 34.2 and 41.8 nF cm−2, respectively (Supplementary Fig. 7c). The AD-MXene was coated on ZTO active layer as source/drain electrodes, after which PVDF-HFP or FPVDF-HFP was coated to form the dielectric layer. The EHD printing of AD-MXene as a gate electrode completed the fabrication of TFT with top-gate top-contact geometry, as the illustration and optical microscope images of devices shown in Fig. 4a. The transfer properties of TFTs with PVDF-HFP or FPVDF-HFP dielectrics were obtained in the saturation regime with VG sweep (±5 V) under VD of 5 V. In contrast to a counter-clockwise hysteresis displayed by the TFT with PVDF-HFP dielectric, no hysteresis was observed for the TFT with FPVDF-HFP dielectric. Due to their high dielectric constant (k) values and lack of functional groups that trap charges, PVDF-based polymers are usually employed as dielectrics to fabricate low-voltage-operating electrically stable TFTs56. The ferroelectric behavior of these dielectrics (such as PVDF-HFP), which arises due to the C-F dipoles rearrangement under a strong electric field, results in hysteresis during the operation of TFTs, as shown in Fig. 4b57. The size of the hysteresis can be decreased by controlling the crystallinity and crystallite size of the dielectrics, precisely, by decoupling the ferroelectric domains of dielectrics58. It was demonstrated that the ferroelectric behavior of the PVDF-HFP dielectric can be substantially decreased by adding the FPA-3F cross-linker58,59. Accordingly, negligible hysteresis was observed during the transfer operation of TFT with FPVDF-HFP dielectric layer (Fig. 4c). The electrical parameters of both TFTs, such as μFET, Vth, and ON/OFF current ratio (ION/IOFF) were extracted in the saturation regime of the transfer curves and summarized in Table 1. Positive bias-stress tests were performed on the TFTs to confirm the device reliability, where the Vth of n-type TFTs shifts towards the positive value under the applied positive gate-source voltage (Fig. 4d, e). The transfer characteristics recorded under the continuous applied bias of 5 V revealed TFTs’ good bias stability features. They ascertained the electrical robustness of both PVDF-HFP and FPVDF-HFP dielectrics. Therefore, the fabrication of TFTs with AD-MXene electrodes provides insights into the future manufacturing of MXene-based electronic devices with operational and chemical stability.

Fig. 4: Transfer characteristics and gate bias-stress tests of TFTs with PVDF-HFP or FPVDF-HFP dielectric layers.
figure 4

a Schematic illustration and top-view optical microscope images of top-gate top-contact TFTs consisting of AD-MXene electrodes, ZTO active layer, and PVDF-HFP or FPVDF-HFP dielectric layer. Transfer characteristics (b, c) and gate bias-stress tests (d, e) of the top-gate top-contact TFTs.

Table 1 Electrical parameters of TFTs with PVDF-HFP and FPVDF-HFP dielectric layers

The transfer characteristics of the TFT with FPVDF-HFP dielectric were further investigated after one month of storage under 60% RH at 25 °C, as illustrated in Fig. 5a. Transfer curves (Fig. 5b), bias-stress test results (Fig. 5c, d), and measured parameters in Table 1 revealed that the exposure to relative humidity doesn’t significantly change the electrical performance of the TFT device. In addition to preserving the bias stability feature, the device maintained μFET, ION/IOFF ratio, and Vth values remained close to their initial values even after the exposure of 60% RH for 30 days. All these results confirmed the excellent stability of AD-MXene electrodes under humid conditions. To demonstrate the scalability of TFTs with AD-MXene electrodes, we fabricated a 7-inch wafer-scale TFT array using FPVDF-HFP dielectric. The digital photograph of the TFT array, along with the optical microscope image of an individual device, is displayed in Fig. 6a. All 64 TFTs in the array exhibited stable transfer curves under VG sweep from -5 V to 5 V. Furthermore, good output characteristics, i.e., linear/saturation switching with a stepwise increase in the VG, and excellent bias stability were observed for the TFT devices in the array (Supplementary Fig. 8). The μFET values calculated from the transfer curves of 64 TFTs were distributed in a small range, with an average μFET being 4.42 ± 0.18 cm2 V−1 s−1 (Fig. 6b).

Fig. 5: Stability results of TFTs after exposure to humidity (60% RH at 25 °C).
figure 5

a Schematic showing the endurance test of TFT with AD-MXene electrodes under 60% RH at 25 °C. b Transfer characteristics of the TFT before and after 30 days of storage under 60% RH at 25  °C. Bias-stress stability test in the transfer characteristics of the TFT before (c) and after 30 days of storage (d) under 60% RH at 25 °C.

Fig. 6: Fabrication of TFT device array and their mobilities.
figure 6

a Schematic representation and a digital photograph of an array of 64 TFT devices on a 7-inch wafer, and the optical microscope image of an individual TFT device in the array. b Scattered plot and histogram showing the distribution of μFET values of 64 TFT devices.

Integration of TFTs for the fabrication of logic circuits

To demonstrate the practical applicability of AD-MXene electrodes, a high-performance complementary inverter was fabricated with TFTs comprising AD-MXene electrodes, FPVDF-HFP dielectric, and ZTO active layer. Figure 7a shows the schematic, top-view optical image, and circuit diagram of the complementary inverter fabricated by using two TFTs (load TFT and drive TFT), wherein the load transistor’s gate electrode was connected to the drain electrode, which was used as the power supply voltage (VDD). The typical voltage transfer (input–output) characteristics and corresponding inverter gains were investigated at a VDD of 5 V, as shown in Fig. 7b. Before the switching (or at low input voltage (VIN)), the inverter’s output voltage (VOUT) is almost equal to that of VDD. However, the high VIN enabled the sharp switching of the inverter’s VOUT from a high value to 0 V, and the VOUT was restored to a high value when the VIN decreased back to a low value. This voltage reversal feature of the inverter can transform “1” and “0” input logic states to “0” and “1” output states, respectively. It was also observed that voltage transfer curves of inverters fabricated with FPVDF-HFP dielectric didn’t present any hysteresis feature. This inverter exhibited a significantly higher voltage gain (dVOUT/dVIN) of 17.8.

Fig. 7: Output characteristics of NOT, NAND, and NOR logic gates.
figure 7

a Schematic representation, optical microscope image, and circuit diagram of the fabricated complementary inverter device. b Voltage transfer characteristics and DC voltage gain of the complementary inverter fabricated with AD-MXene electrodes and FPVDF-HFP dielectrics. c Optical microscope images and circuit diagrams of the developed NAND and NOR logic gates. d Input voltages and corresponding output voltage characteristics of NAND and NOR logic gates fabricated with AD-MXene electrodes and FPVDF-HFP dielectric.

The feasibility of prepared TFTs in constructing logic gates was further demonstrated by fabricating NAND and NOR logic gates (Fig. 7c, d). Assembling an additional drive TFT to NOT gate in series and parallel completes the fabrication of NOR and NAND logic gates, respectively. Figure 7c shows top-view optical images and circuit diagrams of NAND and NOR logic gates. The VOUT characteristics of both these logic gates were investigated at low-voltage-operation conditions (~3 V) against different combinations of input signals (VA and VB) (Fig. 7d). When at least one of the drive TFTs is turned OFF by maintaining 0 V input voltage, i.e., at logic input signal combinations of (0, 0), (1, 0), and (0, 1), the VOUT of the NAND logic gate becomes “VDD”, i.e., a logic output signal “1”. In other words, the VOUT of the NAND logic gate becomes “0 V” or logic state “0” if and only if both drive transistors are turned “ON” by applying VA = 3 V and VB = 3 V or the input logic signals combination (1, 1) (Fig. 7d). On the other hand, the VOUT of NOR gate, wherein the drive TFTs are connected in series, becomes a logic state “1” (VOUT = VDD) if and only if both TFTs are turned OFF by maintaining VA = 0 V and VB = 0 V or a logic input signal combination (0, 0). Any other combination of input voltages would turn ON at least one of the TFTs. As a result, the VOUT of the NOR gate becomes logic state “0” (VOUT = 0 V) (Fig. 7d).

Integration of TFTs for the fabrication of 1T1M device

PVDF and its copolymer, PVDF-HFP, are renowned for their ferroelectric behavior, primarily attributed to the reorientation of carbon–fluorine (C–F) dipoles under high electric fields. This trait allows a ferroelectric material to retain its polarization even after removing the electric field. On the other hand, in the case of FPVDF-HFP, which uses fluorophenyl azide to form the cross-links, the reorientation of the atoms was restricted. As a result, removing the electric field eliminated the polarization, allowing for stable driven transistor behavior. The hysteresis observed during the operation of TFT with PVDF-HFP dielectric is identical to that of conventional ferroelectric memory transistors (Fig. 4b). Hence, the feasibility of these TFTs for integrating memory devices was investigated. The transfer characteristics of TFT with PVDF-HFP dielectric were shifted depending on the applied constant positive and negative VG, as shown in Fig. 8a. In detail, shifting towards negative values was noted when increasing the constant positive VG (5 V, 10 V, and 20 V), while shifting towards positive values was noted when increasing the constant negative VG (-5 V, -10 V, and -20 V). Accordingly, the absolute Vth value shift towards positive and negative values increased with an increase in the constant negative and constant positive VG, respectively (Fig. 8b). Different ID values observed at VG = 0 V for constant positive and negative VG can act as ON- and OFF-states of the device, and are helpful for the information programming or erasing. The ON-state current of ≈10−6 A was measured after applying a constant positive voltage of 20 V, while the off-state current of ≈10−10 A was measured after applying a constant negative voltage of −20 V (Fig. 8c, d). The ON-state current allows the device to be programmed for information storage, while the erasing can be achieved with the OFF-state current. Further, upon increasing the erasing pulse width from 0.3 to 2 s, the transfer curve shifted in the positive VG direction. However, this tuning of pulse width didn’t result in any variation corresponding to ID at VG = 0 (Supplementary Fig. S9).

Fig. 8: Transfer characteristics of TFTs under the application of programming and erasing levels.
figure 8

a Transfer characteristics of TFT with AD-MXene electrodes and PVDF-HFP dielectric after applying a negative gate bias (–20 V) for erasing levels and positive gate bias (20 V) for programming levels. b Vth of the TFT after applying different programming and erasing levels. c TFT transfer curves after applying programming (20 V) and erasing levels (–5, –10, and –20 V) for 1 s. d ID values of the TFT at VG = 0 after applying programming (20 V) and erasing levels (–5, –10, and –20 V). The error bars in this figure represent the standard deviations of five parallel tests.

The prepared TFTs with PVDF-HFP and FPVDF-HFP dielectrics were used as memory TFT and control TFT, respectively, for fabricating one-transistor-one-memory (1T1M) cells. The 1T1M architecture was chosen to ensure a non-destructive read-out capability for ferroelectric memory cells. This design offers the advantage of separating the distinct programming/erasing and reading processes of the memory transistor by utilizing the control transistor. Figure 9a shows the schematic representation of the fabricated memory device along with an optical micrograph and circuit diagram. The gate voltage of the memory TFT can be applied depending on the signal of the control TFT. The dynamic behavior of the 1T1M device was examined by implementing multiple writing and reading processes, as shown in Fig. 9b. Programming/erasing and reading operations were distinctively selected by controlling bit line voltage (VBL) signal access to the memory transistor through applying word line voltages (VWL) of 20 V and –20 V, respectively. In detail, the control transistor was turned ON upon applying a VWL of 20 V; subsequently, this action triggered the transfer of the VBL signal to the gate electrode of the memory transistor. In this condition, both programming and erasing operations were accomplished by applying VBL as 20 V and –20 V, respectively. In contrast, the reading of the stored data was performed at VWL = –20 V, wherein the control transistor was turned OFF, and, as a result, the ID of the memory transistor remained at the same state irrespective of the VBL. This fabricated 1T1M cell exhibited good retention and cyclic endurance properties, as shown in Fig. 9c, d, respectively. After adjusting the memory cell to a programming or erasing state, the retention test was performed by monitoring the readout current as a function of time at VWL = −20 V. The device maintained ON and OFF currents for 104 s without much degradation in performance, which specified its high retention capability. The cycling stability test, which was conducted by recording the currents for repeated cycles of programming and erasing processes, revealed the switching stability and reliability of the device (Fig. 9d).

Fig. 9: Dynamic response, retention, and cyclic stability properties of 1T1M cell.
figure 9

a Schematic illustration, optical microscope image, and circuit diagram of the fabricated 1T1M cell. b Dynamic response of the 1T1M cell, i.e., ID as a function of VBL and VWL input signals: VWL = 20 V and WBL = 20 V for programming, VWL = 20 V and WBL = −20 V for erasing, and VWL = −20 V and WBL = 0 V for reading. Retention properties (c) and cyclic stability over 100 cycles (d) of programming/erasing operations of the 1T1M cell.

In summary, we demonstrated the patterning of alkylated 3,4-dihydroxy-L-phenylalanine (ADOPA) ligand functionalized MXene (AD-MXene) dispersions in ethanol by electrohydrodynamic (EHD) printing process. The excellent conductivity and facile processability of AD-MXene lines allowed their utilization as source, drain, and gate electrodes to fabricate all-solution processed thin-film transistors (TFTs) through EHD printing, wherein zinc-tin-oxide and PVDF-HFP or FPVDF-HFP were utilized as active and dielectric layers of TFTs, respectively. The performance of AD-MXene electrodes was higher than that of the vacuum-deposited Au and Al contacts. We demonstrated exceptional stability to TFTs under high humidity conditions due to hydrophobic ADOPA ligands’ ability to restrict moisture ingress. Furthermore, the robust operation of TFTs with AD-MXene electrodes facilitated the fabrications of high-performance complementary logic circuits (complementary inverter, NAND gate, and NOR gate) and a one-transistor-one-memory cell. Overall, this work proves that appropriately designed surface functionalized MXenes provide a pathway to environmentally stable printable MXene-based electronics (MXetronics).



Source link

Leave a Reply

Your email address will not be published. Required fields are marked *

Back To Top